System and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process

ABSTRACT

A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The dielectric layer is etched to create a first anti-fuse contact opening down to the underlying P type silicon and a second anti-fuse contact opening down to the underlying N type silicon. A metal layer is deposited over the tungsten plug and over the dielectric layer and etched to form an anti-fuse metal contact in each of two anti-fuse contact openings. A bias voltage is applied to the anti-fuse metal contacts to activate the anti-fuse.

TECHNICAL FIELD OF THE INVENTION

The present invention is generally directed to the manufacture ofintegrated circuits and, in particular, to a system and method formanufacturing an integrated circuit anti-fuse in conjunction with atungsten plug process.

BACKGROUND OF THE INVENTION

In the manufacture of integrated circuits it is sometimes desirable tocreate an anti-fuse structure. The operation of an anti-fuse is oppositeto the operation of a fuse. When a fuse is operationally activated, theresistance of the fuse decreases from a high level of resistance to alow level of resistance. When an anti-fuse is operationally activated,the resistance of the anti-fuse increases from a low level of resistanceto a high level of resistance.

Examples of prior art anti-fuse structures and methods of theirmanufacture are described in U.S. Pat. No. 6,440,781 and in U.S. Pat.No. 6,563,189. These patents describe prior art anti-fuse structuresthat are used in conjunction with a tungsten plug metallization process.These patents describe prior art methods that employ a tungsten etchbackprocess and a high temperature aluminum deposition to enable a goodcontact fill. The anti-fuse manufacturing processes that are describedin the prior art are compatible with a back end process flow that uses atungsten plug metallization process.

Further progress of integrated circuit technology has made it clear thatprior art anti-fuses and the methods of their manufacture are notconvenient for use in advanced aluminum backend technology nodes.Specifically, the prior art structures and methods are not convenientfor use with advanced aluminum backend technology nodes of 0.35 micronsize or 0.25 micron size. This makes it difficult to port an integratedcircuit device design from an older factory (that uses the prior arttechnology) to a newer factory (that uses advanced aluminum backendtechnology nodes). Use of the prior art structures and methods in anewer factory would require a radical redesign of the integrated circuitdevice or the use of outdated process equipment in the newer factory.

Therefore, there is a need in the art for an improved anti-fusestructure and method of manufacture. There is a need in the art for animproved anti-fuse structure and method of manufacture that allows theporting of an integrated circuit device design from an older technology.There is a need in the art for an improved anti-fuse structure andmethod of manufacture that is compatible with advanced aluminum backendtechnology nodes. There is a need in the art for an improved anti-fusestructure and method of manufacture that can remedy the above describeddeficiencies of prior art anti-fuse technology.

In an advantageous embodiment of the system and method of the presentinvention, a tungsten plug is formed in a dielectric layer that overliesa portion of P type silicon and an adjacent portion of N type silicon.The dielectric layer is etched to create a first anti-fuse contactopening down to the underlying P type silicon and a second anti-fusecontact opening down to the underlying N type silicon. A metal layer isthen deposited over the tungsten plug and over the dielectric layer. Themetal layer is then etched to form a first anti-fuse metal contact inthe first anti-fuse contact opening and to form a second anti-fuse metalcontact in the second anti-fuse contact opening.

A bias voltage is applied to the first and second anti-fuse metalcontacts to activate the anti-fuse. The application of the bias voltagecreates an electrically conductive path from the first anti-fuse metalcontact through the underlying P type silicon and through the underlyingN type silicon to the second anti-fuse metal contact.

Before undertaking the Detailed Description of the Invention below, itmay be advantageous to set forth definitions of certain words andphrases used throughout this patent document: the terms “include” and“comprise,” as well as derivatives thereof, mean inclusion withoutlimitation; the term “or,” is inclusive, meaning and/or; the phrases“associated with” and “associated therewith,” as well as derivativesthereof, may mean to include, be included within, interconnect with,contain, be contained within, connect to or with, couple to or with, becommunicable with, cooperate with, interleave, juxtapose, be proximateto, be bound to or with, have, have a property of, or the like.

Definitions for certain words and phrases are provided throughout thispatent document, those of ordinary skill in the art should understandthat in many, if not most instances, such definitions apply to prioruses, as well as to future uses, of such defined words and phrases.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and itsadvantages, reference is now made to the following description taken inconjunction with the accompanying drawings, in which like referencenumerals represent like parts:

FIG. 1 illustrates a prior art integrated circuit structure thatcomprises a dielectric layer over a silicon layer and a tungsten plugthrough the dielectric layer where the tungsten plug extends down to theunderlying silicon layer;

FIGS. 2 through 4 illustrate cross sectional views showing sequentialsteps in the manufacture of an anti-fuse of the present invention;

FIG. 5 illustrates a cross sectional view that shows an anti-fuse of thepresent invention as shown in FIG. 4 after the anti-fuse has beenoperationally activated;

FIG. 6 illustrates a cross sectional view that shows an anti-fuse of thepresent invention formed under a Local Oxidation of Silicon (LOCOS)isolation structure;

FIG. 7 illustrates a cross sectional view that shows an anti-fuse of thepresent invention as shown in FIG. 6 after the anti-fuse has beenoperationally activated; and

FIG. 8 illustrates a flow chart showing steps of method formanufacturing an anti-fuse of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1 through 8, discussed below, and the various embodiments used todescribe the principles of the present invention in this patent documentare by way of illustration only and should not be construed in any wayto limit the scope of the invention. Those skilled in the art willunderstand that the principles of the present invention may beimplemented with any type of suitably arranged integrated circuit.

FIG. 1 illustrates of a prior art integrated circuit structure 100.Structure 100 comprises a silicon layer 110 and a dielectric layer 120over the silicon layer 110. Conventional means are used to etch anopening through the dielectric layer 120 and fill the opening with atungsten plug 130. A contact salicide 140 is first formed at the bottomof the plug opening and then the plug opening is filled with tungsten toform the tungsten plug 130. The tungsten plug 130 provides a conductiveelectrical path through the dielectric layer 120 to the underlyingsilicon layer 110.

FIGS. 2 through 4 illustrate cross sectional views showing sequentialsteps in the manufacture of an anti-fuse of the present invention. FIG.2 illustrates a cross sectional view of an integrated circuit structure200 that comprises an underlying silicon layer. The underlying siliconlayer comprises a portion of P type silicon 205 and an adjacent portionof N type silicon 210. The portion of P type silicon 205 and the portionof N type silicon 210 are covered with a dielectric layer 220.Conventional means are used to etch an opening through the dielectriclayer 220 and fill the opening with a tungsten plug 230. A contactsalicide 240 is first formed at the bottom of the plug opening and thenthe plug opening is filled with tungsten to form the tungsten plug 230.The tungsten plug 230 provides a conductive electrical path through thedielectric layer 220 to the portion of P type silicon 205.

Then a second mask and etch procedure is used to etch contact openings250 and 260 through the dielectric layer 220 in order to form theanti-fuse contacts of the present invention. Contact opening 250 extendsthrough the dielectric layer 220 down to the underlying portion of Ptype silicon 205. Contact opening 260 extends through the dielectriclayer 220 down to the underlying portion of N type silicon 210.

After a contact etch and clean procedure has been performed to form thecontact openings 250 and 260, a metal deposition procedure is applied tocover the surface of structure 200 with a metal layer 310. The metallayer 310 is shown in FIG. 3. Aluminum is a metal that is typically usedfor the metal layer 310. The metal deposition procedure is applied atthis point in the manufacturing method skipping a step of linerprocessing that is usually applied at this point. No liner orsalicidation steps are performed during the formation of the anti-fusecontacts.

FIG. 3 illustrates a cross sectional view of an integrated circuitstructure 300 of the present invention. The metal layer 310 covers thetop of the tungsten plug 230 and the surface of the dielectric layer220. The metal layer 310 also covers the sides and bottoms of thecontact openings 250 and 260.

In the next step of the method of the present invention a mask and etchprocedure is performed to etch two openings (410 and 420) through metallayer 310. FIG. 4 illustrates a cross sectional view that shows anintegrated circuit structure 400 of the present invention after themetal layer 310 has been etched. As shown in FIG. 4, opening 410 throughthe metal layer 310 is located between the tungsten plug 230 and themetal covered contact opening 250 that extends down to the P typesilicon 205. Opening 410 extends through the metal layer 310 down to thetop of the dielectric layer 220.

Opening 420 through the metal layer 310 is located between the metalcovered contact opening 250 that extends down to the P type silicon 205and the metal covered contact opening 260 that extends down to the Ntype silicon 210. Opening 420 extends through the metal layer 310 downto the top of the dielectric layer 220. As shown in FIG. 4, the locationof opening 420 is over the junction between the P type silicon 205 andthe N type silicon 210.

The integrated circuit structure 400 forms the anti-fuse the presentinvention. The metal covered contact opening 250 that extends down tothe P type silicon 205 forms a first anti-fuse contact 430. The metalcovered contact opening 260 that extends down to the N type silicon 210forms a second anti-fuse contact 440. The electrical path between firstcontact 430 and second contact 440 goes though the P type silicon 205and the N type silicon 210. There is a relatively high electricalresistance at the juncture of the P type silicon 205 and the N typesilicon 210.

When it is desired to maintain the relatively high electrical resistanceof the anti-fuse, then the anti-fuse is left electrically open. Thenother process steps that reduce contact resistance in other areas (notshown) of the integrated circuit device (such as contact salicidationand argon plasma sputter etch clean) are not needed for the anti-fuse.

When it is desired to reduce the relatively high electrical resistanceof the anti-fuse, then the anti-fuse is made operational by applying abias voltage between the first anti-fuse contact 430 and the secondanti-fuse contact 440. A typical bias voltage may have a value offourteen volts (14 V) to twenty two volts (22 V). Application of a biasvoltage to the anti-fuse contacts (430 and 440) is sometimes referred toas “zapping” the anti-fuse.

Application of the bias voltage will form an electrically conductivepath from the first anti-fuse contact 430, and through the P typesilicon 205, and through the N type silicon 210 to the second anti-fusecontact 440. The portion of the electrically conductive path through theP type silicon 205 and the N type silicon 210 is shown in FIG. 5 anddesignated with reference numeral 510. FIG. 5 illustrates a crosssectional view that shows an integrated circuit structure 500 of thepresent invention after the portion 510 of the electrically conductivepath has been formed by applying a bias voltage.

The portion 510 of the electrically conductive path is formed by amelted mix of metal and silicon. When the metal is aluminum, then theportion 510 of the electrically conductive path is formed by a meltedmix of aluminum and silicon. The portion 510 of the electricallyconductive path occurs due to a thermal-electric breakdown of the P typesilicon 205 and the N type silicon 210 that is induced by theapplication of the bias voltage. The portion 510 of the electricallyconductive path creates an electrical short between the first anti-fusecontact 430 and the second anti-fuse contact 440.

When aluminum is used as the metal to fill a contact opening it isindustry practice to use a deposition temperature of at least fourhundred fifty degrees Celsius (450° C.). This relatively hightemperature is used to ensure that the aluminum material fully fills thecontact opening.

In the anti-fuse contact openings (250, 260) of the present invention ithas been discovered that such a high temperature is not required. It hasbeen discovered that a relatively low deposition temperature ofapproximately two hundred seventy five degrees Celsius (275° C.) may besuccessfully used for the aluminum deposition in the anti-fuse contactopenings (250, 260) of the present invention. As shown in FIGS. 3through 5, the aluminum deposition for the anti-fuse contacts of thepresent invention need only partially fill the contact openings (250,260). The expression “partially fill” refers to covering the sides andbottoms of the anti-fuse contact openings (250, 260) with aluminummaterial. The aluminum material need not fully fill the contact openings(250, 260). Therefore, the lower temperature of approximately 275° C.may be successfully used.

The system and method of the present invention can also be used to forman anti-fuse structure in an integrated circuit structure that uses aLOCOS isolation process. The letters “LOCOS” stand for Local Oxidationof Silicon. LOCOS is a well known isolation technique used in oldertechnologies to create an isolation between elements of an integratedcircuit (e.g., transistors).

FIG. 6 illustrates a cross sectional view that shows an integratedcircuit structure 600 of the present invention showing an anti-fuse ofthe present invention formed under a Local Oxidation of Silicon (LOCOS)isolation structure 610. The integrated circuit structure 600 shown inFIG. 6 is the same as the integrated circuit structure 400 shown in FIG.4 except that it comprises LOCOS structure 610. LOCOS structure 610 islocated between the silicon layer (comprising portions 205 and 210) andthe dielectric layer 220. LOCOS structure 610 is located above thejuncture of the P type silicon 205 and the N type silicon 210.

The anti-fuse of structure 600 is made operational by applying a biasvoltage between the first anti-fuse contact 430 and the second anti-fusecontact 440. Application of the bias voltage will form an electricallyconductive path from the first anti-fuse contact 430, and through the Ptype silicon 205 under LOCOS structure 610, and through the N typesilicon 210 under LOCOS structure 610 to the second anti-fuse contact440. The portion of the electrically conductive path through the P typesilicon 205 and the N type silicon 210 is shown in FIG. 7 and designatedwith reference numeral 710. FIG. 7 illustrates a cross sectional viewthat shows an integrated circuit structure 700 of the present inventionafter the portion 710 of the electrically conductive path has beenformed by applying a bias voltage.

FIG. 8 illustrates a flow chart 800 showing steps of method formanufacturing an anti-fuse of the present invention. In the first stepof the method a silicon layer is deposited that comprises a portion of Ptype silicon 205 and an adjacent portion of N type silicon 210 (step810). Then a dielectric layer 220 is deposited over the silicon layer(205,210) (step 820).

Then a mask and etch procedure is performed to etch an opening throughthe dielectric layer 220 to receive a tungsten plug 230 (step 830). Thena contact salicide 240 is formed at the bottom of the tungsten plugopening and the opening is filled with the tungsten plug 230 (step 840).

Then a mask and etch procedure is performed to etch a first anti-fusecontact opening 250 through dielectric layer 220 down to the P typesilicon 205 and to etch a second anti-fuse contact opening 260 throughdielectric layer 220 to the N type silicon 210 (step 850). Then a metallayer 310 is deposited. Aluminum 310 may be deposited at a relativelylow temperature of two hundred seventy five degrees Celsius (275° C.) topartially fill the first anti-fuse contact opening 250 and to partiallyfill the second anti-fuse contact opening 260 (step 860).

Then a mask and etch procedure is performed to etch the metal layer 310down to the dielectric layer 220 to form an opening 410 between thetungsten plug 230 and the first anti-fuse contact opening 250 and toform an opening 420 between the first and second anti-fuse contactopenings (250 and 260) (step 870).

To active the anti-fuse a bias voltage is applied to the first anti-fusecontact 430 of the metal 310 of the first anti-fuse contact opening 250and to the second anti-fuse contact 440 of the metal 310 of the secondanti-fuse contact opening 260 (step 880). The bias voltage forms anelectrically conductive path 510 from the first anti-fuse contact 430through the P type silicon 205 and through the N type silicon 210 and tothe second anti-fuse contact 440 (step 890).

The method of the present invention for manufacturing an anti-fuse in anintegrated circuit is compatible with back end flow processes that areused in 0.35 micron technology and in 0.25 micron technology. The methodof the present invention for manufacturing an anti-fuse in an integratedcircuit is also compatible with advanced aluminum metallizationprocesses.

The method of the present invention uses a mask and etch procedure tocreate a tungsten plug in a dielectric layer that overlies a portion ofP type silicon and a portion of N type silicon. The method then uses amask and etch procedure to create a first anti-fuse contact openingthrough the dielectric layer to the underlying P type silicon and asecond anti-fuse contact opening through the dielectric layer to theunderlying N type silicon. The mask and etch procedure that creates thefirst and second anti-fuse contact openings does not require the use ofsalicidation and liner formation that are used in prior art methods.

The foregoing description has outlined in detail the features andtechnical advantages of the present invention so that persons who areskilled in the art may understand the advantages of the invention.Persons who are skilled in the art should appreciate that they mayreadily use the conception and the specific embodiment of the inventionthat is disclosed as a basis for modifying or designing other structuresfor carrying out the same purposes of the present invention. Persons whoare skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the inventionin its broadest form.

Although the present invention has been described with an exemplaryembodiment, various changes and modifications may be suggested to oneskilled in the art. It is intended that the present invention encompasssuch changes and modifications as fall within the scope of the appendedclaims.

1-16. (canceled)
 17. An anti-fuse in an integrated circuit comprising: asilicon layer that comprises a portion of P type silicon and an adjacentportion of N type silicon; a dielectric layer over the silicon layer;and a tungsten plug through the dielectric layer, the tungsten plug isin electrical contact with the portion of P type silicon; wherein thedielectric layer has a first contact opening through the dielectriclayer down to the portion of P type silicon; and wherein the dielectriclayer has a second contact opening through the dielectric layer down tothe adjacent portion of N type silicon.
 18. The anti-fuse as claimed inclaim 17, further comprising: a metal layer over the etched dielectriclayer, over the tungsten plug, over the portion of P type silicon, andover the adjacent portion of N type silicon.
 19. The anti-fuse asclaimed in claim 18, wherein: the metal layer comprises a first portionthat forms a first anti-fuse contact in electrical contact with theportion of P type silicon; and the metal layer comprises a secondportion that forms a second anti-fuse contact in electrical contact withthe portion of N type silicon.
 20. The anti-fuse as claimed in claim 19,further comprising: an electrically conductive path from the firstanti-fuse contact through the portion of P type silicon and through theadjacent portion of N type silicon to the second anti-fuse contact. 21.The anti-fuse as claimed in claim 20, wherein the electricallyconductive path through the portion of P type silicon and through theportion of N type silicon passes under a LOCOS isolation structurelocated at a junction between the portion of P type silicon and theportion of N type silicon.
 22. The anti-fuse as claimed in claim 19,wherein the metal layer comprises a third portion separate from thefirst and second portions of the metal layer, the third portion of themetal layer in electrical contact with the tungsten plug.
 23. Theanti-fuse as claimed in claim 19, wherein: the first portion of themetal layer comprises aluminum partially filling the first contactopening; and the second portion of the metal layer comprises aluminumpartially filling the second contact opening.
 24. The anti-fuse asclaimed in claim 19, wherein the first and second portions of the metallayer are separated by an opening located over a junction between theportion of P type silicon and the portion of N type silicon.
 25. Theanti-fuse as claimed in claim 17, further comprising: a contact salicideat a bottom of the first contact opening.
 26. An anti-fuse in anintegrated circuit comprising: a silicon layer that comprises a portionof P type silicon and an adjacent portion of N type silicon in physicalcontact with the portion of P type silicon; a dielectric layer over thesilicon layer, wherein the dielectric layer has a first contact openingthrough the dielectric layer to the portion of P type silicon, andwherein the dielectric layer has a second contact opening through thedielectric layer to the portion of N type silicon; a conductive plugthrough the dielectric layer, wherein the conductive plug is inelectrical contact with the portion of P type silicon; and a conductivelayer comprising (i) a first portion that forms a first anti-fusecontact through the first contact opening in electrical contact with theportion of P type silicon and (ii) a second portion that form a secondanti-fuse contact through the second contact opening in electricalcontact with the portion of N type silicon.
 27. The anti-fuse as claimedin claim 26, further comprising: an electrically conductive path fromthe first anti-fuse contact through the portion of P type silicon andthrough the portion of N type silicon to the second anti-fuse contact.28. The anti-fuse as claimed in claim 27, wherein the electricallyconductive path through the portion of P type silicon and through theportion of N type silicon passes under a LOCOS isolation structurelocated at a junction between the portion of P type silicon and theportion of N type silicon.
 29. The anti-fuse as claimed in claim 26,wherein the conductive layer further comprises a third portion separatefrom the first and second portions of the conductive layer, the thirdportion of the conductive layer in electrical contact with theconductive plug.
 30. The anti-fuse as claimed in claim 26, furthercomprising: a contact salicide at a bottom of the first contact opening.31. The anti-fuse as claimed in claim 26, wherein: the first portion ofthe conductive layer comprises aluminum partially filling the firstcontact opening; and the second portion of the conductive layercomprises aluminum partially filling the second contact opening.
 32. Theanti-fuse as claimed in claim 26, wherein the first and second portionsof the conductive layer are separated by an opening located over ajunction between the portion of P type silicon and the portion of N typesilicon.
 33. An anti-fuse in an integrated circuit comprising: asemiconductor layer comprising a portion of P type semiconductor and anadjacent portion of N type semiconductor in physical contact with theportion of P type semiconductor; a dielectric layer over thesemiconductor layer; a conductive plug through the dielectric layer,wherein the conductive plug is in electrical contact with the portion ofP type semiconductor; and a conductive layer over the dielectric layerand over the semiconductor layer, the conductive layer comprising (i) afirst portion that forms a first anti-fuse contact through a firstcontact opening of the dielectric layer in electrical contact with theportion of P type semiconductor and (ii) a second portion that forms asecond anti-fuse contact through a second contact opening of thedielectric layer in electrical contact with the portion of N typesemiconductor.
 34. The anti-fuse as claimed in claim 33, wherein thefirst and second portions of the conductive layer are separated by anopening located over a junction between the portion of P typesemiconductor and the portion of N type semiconductor.
 35. The anti-fuseof claim 33, further comprising: an electrically conductive path fromthe first anti-fuse contact through the portion of P type semiconductorand through the portion of N type semiconductor to the second anti-fusecontact.
 36. The anti-fuse as claimed in claim 35, wherein theelectrically conductive path through the portion of P type semiconductorand through the portion of N type semiconductor passes under a LOCOSisolation structure located at a junction between the portion of P typesemiconductor and the portion of N type semiconductor.